Xenomai API: ksrc/drivers/analogy/national_instruments/ni

00001 
00021 #ifndef __ANALOGY_NI_TIO_H__
00022 #define __ANALOGY_NI_TIO_H__
00023 
00024 #include <analogy/analogy_driver.h>
00025 
00026 #ifdef CONFIG_PCI
00027 #include "mite.h"
00028 #endif
00029 
00030 enum ni_gpct_register {
00031         NITIO_G0_Autoincrement_Reg,
00032         NITIO_G1_Autoincrement_Reg,
00033         NITIO_G2_Autoincrement_Reg,
00034         NITIO_G3_Autoincrement_Reg,
00035         NITIO_G0_Command_Reg,
00036         NITIO_G1_Command_Reg,
00037         NITIO_G2_Command_Reg,
00038         NITIO_G3_Command_Reg,
00039         NITIO_G0_HW_Save_Reg,
00040         NITIO_G1_HW_Save_Reg,
00041         NITIO_G2_HW_Save_Reg,
00042         NITIO_G3_HW_Save_Reg,
00043         NITIO_G0_SW_Save_Reg,
00044         NITIO_G1_SW_Save_Reg,
00045         NITIO_G2_SW_Save_Reg,
00046         NITIO_G3_SW_Save_Reg,
00047         NITIO_G0_Mode_Reg,
00048         NITIO_G1_Mode_Reg,
00049         NITIO_G2_Mode_Reg,
00050         NITIO_G3_Mode_Reg,
00051         NITIO_G0_LoadA_Reg,
00052         NITIO_G1_LoadA_Reg,
00053         NITIO_G2_LoadA_Reg,
00054         NITIO_G3_LoadA_Reg,
00055         NITIO_G0_LoadB_Reg,
00056         NITIO_G1_LoadB_Reg,
00057         NITIO_G2_LoadB_Reg,
00058         NITIO_G3_LoadB_Reg,
00059         NITIO_G0_Input_Select_Reg,
00060         NITIO_G1_Input_Select_Reg,
00061         NITIO_G2_Input_Select_Reg,
00062         NITIO_G3_Input_Select_Reg,
00063         NITIO_G0_Counting_Mode_Reg,
00064         NITIO_G1_Counting_Mode_Reg,
00065         NITIO_G2_Counting_Mode_Reg,
00066         NITIO_G3_Counting_Mode_Reg,
00067         NITIO_G0_Second_Gate_Reg,
00068         NITIO_G1_Second_Gate_Reg,
00069         NITIO_G2_Second_Gate_Reg,
00070         NITIO_G3_Second_Gate_Reg,
00071         NITIO_G01_Status_Reg,
00072         NITIO_G23_Status_Reg,
00073         NITIO_G01_Joint_Reset_Reg,
00074         NITIO_G23_Joint_Reset_Reg,
00075         NITIO_G01_Joint_Status1_Reg,
00076         NITIO_G23_Joint_Status1_Reg,
00077         NITIO_G01_Joint_Status2_Reg,
00078         NITIO_G23_Joint_Status2_Reg,
00079         NITIO_G0_DMA_Config_Reg,
00080         NITIO_G1_DMA_Config_Reg,
00081         NITIO_G2_DMA_Config_Reg,
00082         NITIO_G3_DMA_Config_Reg,
00083         NITIO_G0_DMA_Status_Reg,
00084         NITIO_G1_DMA_Status_Reg,
00085         NITIO_G2_DMA_Status_Reg,
00086         NITIO_G3_DMA_Status_Reg,
00087         NITIO_G0_ABZ_Reg,
00088         NITIO_G1_ABZ_Reg,
00089         NITIO_G0_Interrupt_Acknowledge_Reg,
00090         NITIO_G1_Interrupt_Acknowledge_Reg,
00091         NITIO_G2_Interrupt_Acknowledge_Reg,
00092         NITIO_G3_Interrupt_Acknowledge_Reg,
00093         NITIO_G0_Status_Reg,
00094         NITIO_G1_Status_Reg,
00095         NITIO_G2_Status_Reg,
00096         NITIO_G3_Status_Reg,
00097         NITIO_G0_Interrupt_Enable_Reg,
00098         NITIO_G1_Interrupt_Enable_Reg,
00099         NITIO_G2_Interrupt_Enable_Reg,
00100         NITIO_G3_Interrupt_Enable_Reg,
00101         NITIO_Num_Registers,
00102 };
00103 
00104 static inline enum ni_gpct_register NITIO_Gi_Autoincrement_Reg(unsigned
00105         counter_index)
00106 {
00107         switch (counter_index) {
00108         case 0:
00109                 return NITIO_G0_Autoincrement_Reg;
00110                 break;
00111         case 1:
00112                 return NITIO_G1_Autoincrement_Reg;
00113                 break;
00114         case 2:
00115                 return NITIO_G2_Autoincrement_Reg;
00116                 break;
00117         case 3:
00118                 return NITIO_G3_Autoincrement_Reg;
00119                 break;
00120         default:
00121                 BUG();
00122                 break;
00123         }
00124         return 0;
00125 }
00126 
00127 static inline enum ni_gpct_register NITIO_Gi_Command_Reg(unsigned counter_index)
00128 {
00129         switch (counter_index) {
00130         case 0:
00131                 return NITIO_G0_Command_Reg;
00132                 break;
00133         case 1:
00134                 return NITIO_G1_Command_Reg;
00135                 break;
00136         case 2:
00137                 return NITIO_G2_Command_Reg;
00138                 break;
00139         case 3:
00140                 return NITIO_G3_Command_Reg;
00141                 break;
00142         default:
00143                 BUG();
00144                 break;
00145         }
00146         return 0;
00147 }
00148 
00149 static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned
00150         counter_index)
00151 {
00152         switch (counter_index) {
00153         case 0:
00154                 return NITIO_G0_Counting_Mode_Reg;
00155                 break;
00156         case 1:
00157                 return NITIO_G1_Counting_Mode_Reg;
00158                 break;
00159         case 2:
00160                 return NITIO_G2_Counting_Mode_Reg;
00161                 break;
00162         case 3:
00163                 return NITIO_G3_Counting_Mode_Reg;
00164                 break;
00165         default:
00166                 BUG();
00167                 break;
00168         }
00169         return 0;
00170 }
00171 
00172 static inline enum ni_gpct_register NITIO_Gi_Input_Select_Reg(unsigned
00173         counter_index)
00174 {
00175         switch (counter_index) {
00176         case 0:
00177                 return NITIO_G0_Input_Select_Reg;
00178                 break;
00179         case 1:
00180                 return NITIO_G1_Input_Select_Reg;
00181                 break;
00182         case 2:
00183                 return NITIO_G2_Input_Select_Reg;
00184                 break;
00185         case 3:
00186                 return NITIO_G3_Input_Select_Reg;
00187                 break;
00188         default:
00189                 BUG();
00190                 break;
00191         }
00192         return 0;
00193 }
00194 
00195 static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned
00196         counter_index)
00197 {
00198         switch (counter_index) {
00199         case 0:
00200         case 1:
00201                 return NITIO_G01_Joint_Reset_Reg;
00202                 break;
00203         case 2:
00204         case 3:
00205                 return NITIO_G23_Joint_Reset_Reg;
00206                 break;
00207         default:
00208                 BUG();
00209                 break;
00210         }
00211         return 0;
00212 }
00213 
00214 static inline enum ni_gpct_register NITIO_Gxx_Joint_Status1_Reg(unsigned
00215         counter_index)
00216 {
00217         switch (counter_index) {
00218         case 0:
00219         case 1:
00220                 return NITIO_G01_Joint_Status1_Reg;
00221                 break;
00222         case 2:
00223         case 3:
00224                 return NITIO_G23_Joint_Status1_Reg;
00225                 break;
00226         default:
00227                 BUG();
00228                 break;
00229         }
00230         return 0;
00231 }
00232 
00233 static inline enum ni_gpct_register NITIO_Gxx_Joint_Status2_Reg(unsigned
00234         counter_index)
00235 {
00236         switch (counter_index) {
00237         case 0:
00238         case 1:
00239                 return NITIO_G01_Joint_Status2_Reg;
00240                 break;
00241         case 2:
00242         case 3:
00243                 return NITIO_G23_Joint_Status2_Reg;
00244                 break;
00245         default:
00246                 BUG();
00247                 break;
00248         }
00249         return 0;
00250 }
00251 
00252 static inline enum ni_gpct_register NITIO_Gxx_Status_Reg(unsigned counter_index)
00253 {
00254         switch (counter_index) {
00255         case 0:
00256         case 1:
00257                 return NITIO_G01_Status_Reg;
00258                 break;
00259         case 2:
00260         case 3:
00261                 return NITIO_G23_Status_Reg;
00262                 break;
00263         default:
00264                 BUG();
00265                 break;
00266         }
00267         return 0;
00268 }
00269 
00270 static inline enum ni_gpct_register NITIO_Gi_LoadA_Reg(unsigned counter_index)
00271 {
00272         switch (counter_index) {
00273         case 0:
00274                 return NITIO_G0_LoadA_Reg;
00275                 break;
00276         case 1:
00277                 return NITIO_G1_LoadA_Reg;
00278                 break;
00279         case 2:
00280                 return NITIO_G2_LoadA_Reg;
00281                 break;
00282         case 3:
00283                 return NITIO_G3_LoadA_Reg;
00284                 break;
00285         default:
00286                 BUG();
00287                 break;
00288         }
00289         return 0;
00290 }
00291 
00292 static inline enum ni_gpct_register NITIO_Gi_LoadB_Reg(unsigned counter_index)
00293 {
00294         switch (counter_index) {
00295         case 0:
00296                 return NITIO_G0_LoadB_Reg;
00297                 break;
00298         case 1:
00299                 return NITIO_G1_LoadB_Reg;
00300                 break;
00301         case 2:
00302                 return NITIO_G2_LoadB_Reg;
00303                 break;
00304         case 3:
00305                 return NITIO_G3_LoadB_Reg;
00306                 break;
00307         default:
00308                 BUG();
00309                 break;
00310         }
00311         return 0;
00312 }
00313 
00314 static inline enum ni_gpct_register NITIO_Gi_Mode_Reg(unsigned counter_index)
00315 {
00316         switch (counter_index) {
00317         case 0:
00318                 return NITIO_G0_Mode_Reg;
00319                 break;
00320         case 1:
00321                 return NITIO_G1_Mode_Reg;
00322                 break;
00323         case 2:
00324                 return NITIO_G2_Mode_Reg;
00325                 break;
00326         case 3:
00327                 return NITIO_G3_Mode_Reg;
00328                 break;
00329         default:
00330                 BUG();
00331                 break;
00332         }
00333         return 0;
00334 }
00335 
00336 static inline enum ni_gpct_register NITIO_Gi_SW_Save_Reg(int counter_index)
00337 {
00338         switch (counter_index) {
00339         case 0:
00340                 return NITIO_G0_SW_Save_Reg;
00341                 break;
00342         case 1:
00343                 return NITIO_G1_SW_Save_Reg;
00344                 break;
00345         case 2:
00346                 return NITIO_G2_SW_Save_Reg;
00347                 break;
00348         case 3:
00349                 return NITIO_G3_SW_Save_Reg;
00350                 break;
00351         default:
00352                 BUG();
00353                 break;
00354         }
00355         return 0;
00356 }
00357 
00358 static inline enum ni_gpct_register NITIO_Gi_Second_Gate_Reg(int counter_index)
00359 {
00360         switch (counter_index) {
00361         case 0:
00362                 return NITIO_G0_Second_Gate_Reg;
00363                 break;
00364         case 1:
00365                 return NITIO_G1_Second_Gate_Reg;
00366                 break;
00367         case 2:
00368                 return NITIO_G2_Second_Gate_Reg;
00369                 break;
00370         case 3:
00371                 return NITIO_G3_Second_Gate_Reg;
00372                 break;
00373         default:
00374                 BUG();
00375                 break;
00376         }
00377         return 0;
00378 }
00379 
00380 static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(int counter_index)
00381 {
00382         switch (counter_index) {
00383         case 0:
00384                 return NITIO_G0_DMA_Config_Reg;
00385                 break;
00386         case 1:
00387                 return NITIO_G1_DMA_Config_Reg;
00388                 break;
00389         case 2:
00390                 return NITIO_G2_DMA_Config_Reg;
00391                 break;
00392         case 3:
00393                 return NITIO_G3_DMA_Config_Reg;
00394                 break;
00395         default:
00396                 BUG();
00397                 break;
00398         }
00399         return 0;
00400 }
00401 
00402 static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(int counter_index)
00403 {
00404         switch (counter_index) {
00405         case 0:
00406                 return NITIO_G0_DMA_Status_Reg;
00407                 break;
00408         case 1:
00409                 return NITIO_G1_DMA_Status_Reg;
00410                 break;
00411         case 2:
00412                 return NITIO_G2_DMA_Status_Reg;
00413                 break;
00414         case 3:
00415                 return NITIO_G3_DMA_Status_Reg;
00416                 break;
00417         default:
00418                 BUG();
00419                 break;
00420         }
00421         return 0;
00422 }
00423 
00424 static inline enum ni_gpct_register NITIO_Gi_ABZ_Reg(int counter_index)
00425 {
00426         switch (counter_index) {
00427         case 0:
00428                 return NITIO_G0_ABZ_Reg;
00429                 break;
00430         case 1:
00431                 return NITIO_G1_ABZ_Reg;
00432                 break;
00433         default:
00434                 BUG();
00435                 break;
00436         }
00437         return 0;
00438 }
00439 
00440 static inline enum ni_gpct_register NITIO_Gi_Interrupt_Acknowledge_Reg(int
00441         counter_index)
00442 {
00443         switch (counter_index) {
00444         case 0:
00445                 return NITIO_G0_Interrupt_Acknowledge_Reg;
00446                 break;
00447         case 1:
00448                 return NITIO_G1_Interrupt_Acknowledge_Reg;
00449                 break;
00450         case 2:
00451                 return NITIO_G2_Interrupt_Acknowledge_Reg;
00452                 break;
00453         case 3:
00454                 return NITIO_G3_Interrupt_Acknowledge_Reg;
00455                 break;
00456         default:
00457                 BUG();
00458                 break;
00459         }
00460         return 0;
00461 }
00462 
00463 static inline enum ni_gpct_register NITIO_Gi_Status_Reg(int counter_index)
00464 {
00465         switch (counter_index) {
00466         case 0:
00467                 return NITIO_G0_Status_Reg;
00468                 break;
00469         case 1:
00470                 return NITIO_G1_Status_Reg;
00471                 break;
00472         case 2:
00473                 return NITIO_G2_Status_Reg;
00474                 break;
00475         case 3:
00476                 return NITIO_G3_Status_Reg;
00477                 break;
00478         default:
00479                 BUG();
00480                 break;
00481         }
00482         return 0;
00483 }
00484 
00485 static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(int
00486         counter_index)
00487 {
00488         switch (counter_index) {
00489         case 0:
00490                 return NITIO_G0_Interrupt_Enable_Reg;
00491                 break;
00492         case 1:
00493                 return NITIO_G1_Interrupt_Enable_Reg;
00494                 break;
00495         case 2:
00496                 return NITIO_G2_Interrupt_Enable_Reg;
00497                 break;
00498         case 3:
00499                 return NITIO_G3_Interrupt_Enable_Reg;
00500                 break;
00501         default:
00502                 BUG();
00503                 break;
00504         }
00505         return 0;
00506 }
00507 
00508 enum ni_gpct_variant {
00509         ni_gpct_variant_e_series,
00510         ni_gpct_variant_m_series,
00511         ni_gpct_variant_660x
00512 };
00513 
00514 struct ni_gpct {
00515         struct ni_gpct_device *counter_dev;
00516         unsigned counter_index;
00517         unsigned chip_index;
00518         uint64_t clock_period_ps; /* clock period in picoseconds */
00519         struct mite_channel *mite_chan;
00520         a4l_lock_t lock;
00521 };
00522 
00523 struct ni_gpct_device {
00524         a4l_dev_t *dev;
00525         void (*write_register)(struct ni_gpct * counter,
00526                                 unsigned int bits, enum ni_gpct_register reg);
00527         unsigned (*read_register)(struct ni_gpct * counter,
00528                                    enum ni_gpct_register reg);
00529         enum ni_gpct_variant variant;
00530         struct ni_gpct **counters;
00531         unsigned num_counters;
00532         unsigned regs[NITIO_Num_Registers];
00533         a4l_lock_t regs_lock;
00534 };
00535 
00536 #define Gi_Auto_Increment_Mask          0xff
00537 #define Gi_Up_Down_Shift                5
00538 
00539 #define Gi_Arm_Bit                      0x1
00540 #define Gi_Save_Trace_Bit               0x2
00541 #define Gi_Load_Bit                     0x4
00542 #define Gi_Disarm_Bit                   0x10
00543 #define Gi_Up_Down_Mask                 (0x3 << Gi_Up_Down_Shift)
00544 #define Gi_Always_Down_Bits             (0x0 << Gi_Up_Down_Shift)
00545 #define Gi_Always_Up_Bits               (0x1 << Gi_Up_Down_Shift)
00546 #define Gi_Up_Down_Hardware_IO_Bits     (0x2 << Gi_Up_Down_Shift)
00547 #define Gi_Up_Down_Hardware_Gate_Bits   (0x3 << Gi_Up_Down_Shift)
00548 #define Gi_Write_Switch_Bit             0x80
00549 #define Gi_Synchronize_Gate_Bit         0x100
00550 #define Gi_Little_Big_Endian_Bit        0x200
00551 #define Gi_Bank_Switch_Start_Bit        0x400
00552 #define Gi_Bank_Switch_Mode_Bit         0x800
00553 #define Gi_Bank_Switch_Enable_Bit       0x1000
00554 #define Gi_Arm_Copy_Bit                 0x2000
00555 #define Gi_Save_Trace_Copy_Bit          0x4000
00556 #define Gi_Disarm_Copy_Bit              0x8000
00557 
00558 #define Gi_Index_Phase_Bitshift         5
00559 #define Gi_HW_Arm_Select_Shift          8
00560 
00561 #define Gi_Counting_Mode_Mask           0x7
00562 #define Gi_Counting_Mode_Normal_Bits    0x0
00563 #define Gi_Counting_Mode_QuadratureX1_Bits 0x1
00564 #define Gi_Counting_Mode_QuadratureX2_Bits 0x2
00565 #define Gi_Counting_Mode_QuadratureX4_Bits 0x3
00566 #define Gi_Counting_Mode_Two_Pulse_Bits 0x4
00567 #define Gi_Counting_Mode_Sync_Source_Bits 0x6
00568 #define Gi_Index_Mode_Bit               0x10
00569 #define Gi_Index_Phase_Mask             (0x3 << Gi_Index_Phase_Bitshift)
00570 #define Gi_Index_Phase_LowA_LowB        (0x0 << Gi_Index_Phase_Bitshift)
00571 #define Gi_Index_Phase_LowA_HighB       (0x1 << Gi_Index_Phase_Bitshift)
00572 #define Gi_Index_Phase_HighA_LowB       (0x2 << Gi_Index_Phase_Bitshift)
00573 #define Gi_Index_Phase_HighA_HighB      (0x3 << Gi_Index_Phase_Bitshift)
00574 
00575 /* From m-series example code,
00576    not documented in 660x register level manual */
00577 #define Gi_HW_Arm_Enable_Bit            0x80
00578 /* From m-series example code,
00579    not documented in 660x register level manual */
00580 #define Gi_660x_HW_Arm_Select_Mask      (0x7 << Gi_HW_Arm_Select_Shift)
00581 #define Gi_660x_Prescale_X8_Bit         0x1000
00582 #define Gi_M_Series_Prescale_X8_Bit     0x2000
00583 #define Gi_M_Series_HW_Arm_Select_Mask  (0x1f << Gi_HW_Arm_Select_Shift)
00584 /* Must be set for clocks over 40MHz,
00585    which includes synchronous counting and quadrature modes */
00586 #define Gi_660x_Alternate_Sync_Bit      0x2000
00587 #define Gi_M_Series_Alternate_Sync_Bit  0x4000
00588 /* From m-series example code,
00589    not documented in 660x register level manual */
00590 #define Gi_660x_Prescale_X2_Bit         0x4000
00591 #define Gi_M_Series_Prescale_X2_Bit     0x8000
00592 
00593 static inline unsigned int Gi_Alternate_Sync_Bit(enum ni_gpct_variant variant)
00594 {
00595         switch (variant) {
00596         case ni_gpct_variant_e_series:
00597                 return 0;
00598                 break;
00599         case ni_gpct_variant_m_series:
00600                 return Gi_M_Series_Alternate_Sync_Bit;
00601                 break;
00602         case ni_gpct_variant_660x:
00603                 return Gi_660x_Alternate_Sync_Bit;
00604                 break;
00605         default:
00606                 BUG();
00607                 break;
00608         }
00609         return 0;
00610 }
00611 
00612 static inline unsigned int Gi_Prescale_X2_Bit(enum ni_gpct_variant variant)
00613 {
00614         switch (variant) {
00615         case ni_gpct_variant_e_series:
00616                 return 0;
00617                 break;
00618         case ni_gpct_variant_m_series:
00619                 return Gi_M_Series_Prescale_X2_Bit;
00620                 break;
00621         case ni_gpct_variant_660x:
00622                 return Gi_660x_Prescale_X2_Bit;
00623                 break;
00624         default:
00625                 BUG();
00626                 break;
00627         }
00628         return 0;
00629 }
00630 
00631 static inline unsigned int Gi_Prescale_X8_Bit(enum ni_gpct_variant variant)
00632 {
00633         switch (variant) {
00634         case ni_gpct_variant_e_series:
00635                 return 0;
00636                 break;
00637         case ni_gpct_variant_m_series:
00638                 return Gi_M_Series_Prescale_X8_Bit;
00639                 break;
00640         case ni_gpct_variant_660x:
00641                 return Gi_660x_Prescale_X8_Bit;
00642                 break;
00643         default:
00644                 BUG();
00645                 break;
00646         }
00647         return 0;
00648 }
00649 
00650 static inline unsigned int Gi_HW_Arm_Select_Mask(enum ni_gpct_variant variant)
00651 {
00652         switch (variant) {
00653         case ni_gpct_variant_e_series:
00654                 return 0;
00655                 break;
00656         case ni_gpct_variant_m_series:
00657                 return Gi_M_Series_HW_Arm_Select_Mask;
00658                 break;
00659         case ni_gpct_variant_660x:
00660                 return Gi_660x_HW_Arm_Select_Mask;
00661                 break;
00662         default:
00663                 BUG();
00664                 break;
00665         }
00666         return 0;
00667 }
00668 
00669 #define NI_660x_Timebase_1_Clock        0x0 /* 20MHz */
00670 #define NI_660x_Source_Pin_i_Clock      0x1
00671 #define NI_660x_Next_Gate_Clock         0xa
00672 #define NI_660x_Timebase_2_Clock        0x12 /* 100KHz */
00673 #define NI_660x_Next_TC_Clock           0x13
00674 #define NI_660x_Timebase_3_Clock        0x1e /* 80MHz */
00675 #define NI_660x_Logic_Low_Clock         0x1f
00676 
00677 #define ni_660x_max_rtsi_channel        6
00678 #define ni_660x_max_source_pin          7
00679 
00680 static inline unsigned int NI_660x_RTSI_Clock(unsigned int n)
00681 {
00682         BUG_ON(n > ni_660x_max_rtsi_channel);
00683         return (0xb + n);
00684 }
00685 
00686 static inline unsigned int NI_660x_Source_Pin_Clock(unsigned int n)
00687 {
00688         BUG_ON(n > ni_660x_max_source_pin);
00689         return (0x2 + n);
00690 }
00691 
00692 /* Clock sources for ni e and m series boards,
00693    get bits with Gi_Source_Select_Bits() */
00694 #define NI_M_Series_Timebase_1_Clock    0x0 /* 20MHz */
00695 #define NI_M_Series_Timebase_2_Clock    0x12 /* 100KHz */
00696 #define NI_M_Series_Next_TC_Clock       0x13
00697 #define NI_M_Series_Next_Gate_Clock     0x14 /* when Gi_Src_SubSelect = 0 */
00698 #define NI_M_Series_PXI_Star_Trigger_Clock 0x14 /* when Gi_Src_SubSelect = 1 */
00699 #define NI_M_Series_PXI10_Clock         0x1d
00700 #define NI_M_Series_Timebase_3_Clock    0x1e /* 80MHz, when Gi_Src_SubSelect = 0 */
00701 #define NI_M_Series_Analog_Trigger_Out_Clock 0x1e /* when Gi_Src_SubSelect = 1 */
00702 #define NI_M_Series_Logic_Low_Clock     0x1f
00703 
00704 #define ni_m_series_max_pfi_channel     15
00705 #define ni_m_series_max_rtsi_channel    7
00706 
00707 static inline unsigned int NI_M_Series_PFI_Clock(unsigned int n)
00708 {
00709         BUG_ON(n > ni_m_series_max_pfi_channel);
00710         if (n < 10)
00711                 return 1 + n;
00712         else
00713                 return 0xb + n;
00714 }
00715 
00716 static inline unsigned int NI_M_Series_RTSI_Clock(unsigned int n)
00717 {
00718         BUG_ON(n > ni_m_series_max_rtsi_channel);
00719         if (n == 7)
00720                 return 0x1b;
00721         else
00722                 return 0xb + n;
00723 }
00724 
00725 #define NI_660x_Source_Pin_i_Gate_Select 0x0
00726 #define NI_660x_Gate_Pin_i_Gate_Select  0x1
00727 #define NI_660x_Next_SRC_Gate_Select    0xa
00728 #define NI_660x_Next_Out_Gate_Select    0x14
00729 #define NI_660x_Logic_Low_Gate_Select   0x1f
00730 #define ni_660x_max_gate_pin 7
00731 
00732 static inline unsigned int NI_660x_Gate_Pin_Gate_Select(unsigned int n)
00733 {
00734         BUG_ON(n > ni_660x_max_gate_pin);
00735         return 0x2 + n;
00736 }
00737 
00738 static inline unsigned int NI_660x_RTSI_Gate_Select(unsigned int n)
00739 {
00740         BUG_ON(n > ni_660x_max_rtsi_channel);
00741         return 0xb + n;
00742 }
00743 
00744 
00745 #define NI_M_Series_Timestamp_Mux_Gate_Select   0x0
00746 #define NI_M_Series_AI_START2_Gate_Select       0x12
00747 #define NI_M_Series_PXI_Star_Trigger_Gate_Select 0x13
00748 #define NI_M_Series_Next_Out_Gate_Select        0x14
00749 #define NI_M_Series_AI_START1_Gate_Select       0x1c
00750 #define NI_M_Series_Next_SRC_Gate_Select        0x1d
00751 #define NI_M_Series_Analog_Trigger_Out_Gate_Select 0x1e
00752 #define NI_M_Series_Logic_Low_Gate_Select       0x1f
00753 
00754 static inline unsigned int NI_M_Series_RTSI_Gate_Select(unsigned int n)
00755 {
00756         BUG_ON(n > ni_m_series_max_rtsi_channel);
00757         if (n == 7)
00758                 return 0x1b;
00759         return 0xb + n;
00760 }
00761 
00762 static inline unsigned int NI_M_Series_PFI_Gate_Select(unsigned int n)
00763 {
00764         BUG_ON(n > ni_m_series_max_pfi_channel);
00765         if (n < 10)
00766                 return 1 + n;
00767         return 0xb + n;
00768 }
00769 
00770 
00771 #define Gi_Source_Select_Shift 2
00772 #define Gi_Gate_Select_Shift 7
00773 
00774 #define Gi_Read_Acknowledges_Irq        0x1 /* not present on 660x */
00775 #define Gi_Write_Acknowledges_Irq       0x2 /* not present on 660x */
00776 #define Gi_Source_Select_Mask           0x7c
00777 #define Gi_Gate_Select_Mask             (0x1f << Gi_Gate_Select_Shift)
00778 #define Gi_Gate_Select_Load_Source_Bit  0x1000
00779 #define Gi_Or_Gate_Bit                  0x2000
00780 #define Gi_Output_Polarity_Bit          0x4000 /* set to invert */
00781 #define Gi_Source_Polarity_Bit          0x8000 /* set to invert */
00782 
00783 #define Gi_Source_Select_Bits(x) ((x << Gi_Source_Select_Shift) & \
00784                                   Gi_Source_Select_Mask)
00785 #define Gi_Gate_Select_Bits(x) ((x << Gi_Gate_Select_Shift) & \
00786                                 Gi_Gate_Select_Mask)
00787 
00788 #define Gi_Gating_Mode_Mask             0x3
00789 #define Gi_Gating_Disabled_Bits         0x0
00790 #define Gi_Level_Gating_Bits            0x1
00791 #define Gi_Rising_Edge_Gating_Bits      0x2
00792 #define Gi_Falling_Edge_Gating_Bits     0x3
00793 #define Gi_Gate_On_Both_Edges_Bit       0x4 /* used in conjunction with
00794                                                rising edge gating mode */
00795 #define Gi_Trigger_Mode_for_Edge_Gate_Mask 0x18
00796 #define Gi_Edge_Gate_Starts_Stops_Bits  0x0
00797 #define Gi_Edge_Gate_Stops_Starts_Bits  0x8
00798 #define Gi_Edge_Gate_Starts_Bits        0x10
00799 #define Gi_Edge_Gate_No_Starts_or_Stops_Bits 0x18
00800 #define Gi_Stop_Mode_Mask               0x60
00801 #define Gi_Stop_on_Gate_Bits            0x00
00802 #define Gi_Stop_on_Gate_or_TC_Bits      0x20
00803 #define Gi_Stop_on_Gate_or_Second_TC_Bits 0x40
00804 #define Gi_Load_Source_Select_Bit       0x80
00805 #define Gi_Output_Mode_Mask             0x300
00806 #define Gi_Output_TC_Pulse_Bits         0x100
00807 #define Gi_Output_TC_Toggle_Bits        0x200
00808 #define Gi_Output_TC_or_Gate_Toggle_Bits 0x300
00809 #define Gi_Counting_Once_Mask           0xc00
00810 #define Gi_No_Hardware_Disarm_Bits      0x000
00811 #define Gi_Disarm_at_TC_Bits            0x400
00812 #define Gi_Disarm_at_Gate_Bits          0x800
00813 #define Gi_Disarm_at_TC_or_Gate_Bits    0xc00
00814 #define Gi_Loading_On_TC_Bit            0x1000
00815 #define Gi_Gate_Polarity_Bit            0x2000
00816 #define Gi_Loading_On_Gate_Bit          0x4000
00817 #define Gi_Reload_Source_Switching_Bit  0x8000
00818 
00819 #define NI_660x_Source_Pin_i_Second_Gate_Select         0x0
00820 #define NI_660x_Up_Down_Pin_i_Second_Gate_Select        0x1
00821 #define NI_660x_Next_SRC_Second_Gate_Select             0xa
00822 #define NI_660x_Next_Out_Second_Gate_Select             0x14
00823 #define NI_660x_Selected_Gate_Second_Gate_Select        0x1e
00824 #define NI_660x_Logic_Low_Second_Gate_Select            0x1f
00825 
00826 #define ni_660x_max_up_down_pin         7
00827 
00828 static inline
00829 unsigned int NI_660x_Up_Down_Pin_Second_Gate_Select(unsigned int n)
00830 {
00831         BUG_ON(n > ni_660x_max_up_down_pin);
00832         return 0x2 + n;
00833 }
00834 static inline
00835 unsigned int NI_660x_RTSI_Second_Gate_Select(unsigned int n)
00836 {
00837         BUG_ON(n > ni_660x_max_rtsi_channel);
00838         return 0xb + n;
00839 }
00840 
00841 #define Gi_Second_Gate_Select_Shift     7
00842 
00843 /*FIXME: m-series has a second gate subselect bit */
00844 /*FIXME: m-series second gate sources are undocumented (by NI)*/
00845 #define Gi_Second_Gate_Mode_Bit         0x1
00846 #define Gi_Second_Gate_Select_Mask      (0x1f << Gi_Second_Gate_Select_Shift)
00847 #define Gi_Second_Gate_Polarity_Bit     0x2000
00848 #define Gi_Second_Gate_Subselect_Bit    0x4000 /* m-series only */
00849 #define Gi_Source_Subselect_Bit         0x8000 /* m-series only */
00850 
00851 static inline
00852 unsigned int Gi_Second_Gate_Select_Bits(unsigned int second_gate_select)
00853 {
00854         return (second_gate_select << Gi_Second_Gate_Select_Shift) &
00855                 Gi_Second_Gate_Select_Mask;
00856 }
00857 
00858 #define G0_Save_Bit             0x1
00859 #define G1_Save_Bit             0x2
00860 #define G0_Counting_Bit         0x4
00861 #define G1_Counting_Bit         0x8
00862 #define G0_Next_Load_Source_Bit 0x10
00863 #define G1_Next_Load_Source_Bit 0x20
00864 #define G0_Stale_Data_Bit       0x40
00865 #define G1_Stale_Data_Bit       0x80
00866 #define G0_Armed_Bit            0x100
00867 #define G1_Armed_Bit            0x200
00868 #define G0_No_Load_Between_Gates_Bit 0x400
00869 #define G1_No_Load_Between_Gates_Bit 0x800
00870 #define G0_TC_Error_Bit         0x1000
00871 #define G1_TC_Error_Bit         0x2000
00872 #define G0_Gate_Error_Bit       0x4000
00873 #define G1_Gate_Error_Bit       0x8000
00874 
00875 static inline unsigned int Gi_Counting_Bit(unsigned int counter_index)
00876 {
00877         if (counter_index % 2)
00878                 return G1_Counting_Bit;
00879         return G0_Counting_Bit;
00880 }
00881 
00882 static inline unsigned int Gi_Armed_Bit(unsigned int counter_index)
00883 {
00884         if (counter_index % 2)
00885                 return G1_Armed_Bit;
00886         return G0_Armed_Bit;
00887 }
00888 
00889 static inline unsigned int Gi_Next_Load_Source_Bit(unsigned counter_index)
00890 {
00891         if (counter_index % 2)
00892                 return G1_Next_Load_Source_Bit;
00893         return G0_Next_Load_Source_Bit;
00894 }
00895 
00896 static inline unsigned int Gi_Stale_Data_Bit(unsigned int counter_index)
00897 {
00898         if (counter_index % 2)
00899                 return G1_Stale_Data_Bit;
00900         return G0_Stale_Data_Bit;
00901 }
00902 
00903 static inline unsigned int Gi_TC_Error_Bit(unsigned int counter_index)
00904 {
00905         if (counter_index % 2)
00906                 return G1_TC_Error_Bit;
00907         return G0_TC_Error_Bit;
00908 }
00909 
00910 static inline unsigned int Gi_Gate_Error_Bit(unsigned int counter_index)
00911 {
00912         if (counter_index % 2)
00913                 return G1_Gate_Error_Bit;
00914         return G0_Gate_Error_Bit;
00915 }
00916 
00917 /* Joint reset register bits */
00918 static inline unsigned Gi_Reset_Bit(unsigned int counter_index)
00919 {
00920         return 0x1 << (2 + (counter_index % 2));
00921 }
00922 
00923 #define G0_Output_Bit           0x1
00924 #define G1_Output_Bit           0x2
00925 #define G0_HW_Save_Bit          0x1000
00926 #define G1_HW_Save_Bit          0x2000
00927 #define G0_Permanent_Stale_Bit  0x4000
00928 #define G1_Permanent_Stale_Bit  0x8000
00929 
00930 static inline unsigned int Gi_Permanent_Stale_Bit(unsigned
00931         counter_index)
00932 {
00933         if (counter_index % 2)
00934                 return G1_Permanent_Stale_Bit;
00935         return G0_Permanent_Stale_Bit;
00936 }
00937 
00938 #define Gi_DMA_Enable_Bit       0x1
00939 #define Gi_DMA_Write_Bit        0x2
00940 #define Gi_DMA_Int_Bit          0x4
00941 
00942 #define Gi_DMA_Readbank_Bit     0x2000
00943 #define Gi_DRQ_Error_Bit        0x4000
00944 #define Gi_DRQ_Status_Bit       0x8000
00945 
00946 #define G0_Gate_Error_Confirm_Bit       0x20
00947 #define G0_TC_Error_Confirm_Bit         0x40
00948 
00949 #define G1_Gate_Error_Confirm_Bit       0x2
00950 #define G1_TC_Error_Confirm_Bit         0x4
00951 
00952 static inline unsigned int Gi_Gate_Error_Confirm_Bit(unsigned int counter_index)
00953 {
00954         if (counter_index % 2)
00955                 return G1_Gate_Error_Confirm_Bit;
00956         return G0_Gate_Error_Confirm_Bit;
00957 }
00958 
00959 static inline unsigned int Gi_TC_Error_Confirm_Bit(unsigned int counter_index)
00960 {
00961         if (counter_index % 2)
00962                 return G1_TC_Error_Confirm_Bit;
00963         return G0_TC_Error_Confirm_Bit;
00964 }
00965 
00966 /* Bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */
00967 #define Gi_TC_Interrupt_Ack_Bit         0x4000
00968 #define Gi_Gate_Interrupt_Ack_Bit       0x8000
00969 
00970 #define Gi_Gate_Interrupt_Bit   0x4
00971 #define Gi_TC_Bit               0x8
00972 #define Gi_Interrupt_Bit        0x8000
00973 
00974 #define G0_TC_Interrupt_Enable_Bit      0x40
00975 #define G0_Gate_Interrupt_Enable_Bit    0x100
00976 
00977 #define G1_TC_Interrupt_Enable_Bit      0x200
00978 #define G1_Gate_Interrupt_Enable_Bit    0x400
00979 
00980 static inline unsigned int Gi_Gate_Interrupt_Enable_Bit(unsigned int counter_index)
00981 {
00982         unsigned int bit;
00983 
00984         if (counter_index % 2) {
00985                 bit = G1_Gate_Interrupt_Enable_Bit;
00986         } else {
00987                 bit = G0_Gate_Interrupt_Enable_Bit;
00988         }
00989         return bit;
00990 }
00991 
00992 #define counter_status_mask (A4L_COUNTER_ARMED | A4L_COUNTER_COUNTING)
00993 
00994 #define NI_USUAL_PFI_SELECT(x)  ((x < 10) ? (0x1 + x) : (0xb + x))
00995 #define NI_USUAL_RTSI_SELECT(x) ((x < 7 ) ? (0xb + x) : (0x1b + x))
00996 
00997 /* Mode bits for NI general-purpose counters, set with
00998    INSN_CONFIG_SET_COUNTER_MODE */
00999 #define NI_GPCT_COUNTING_MODE_SHIFT             16
01000 #define NI_GPCT_INDEX_PHASE_BITSHIFT            20
01001 #define NI_GPCT_COUNTING_DIRECTION_SHIFT        24
01002 
01003 #define NI_GPCT_GATE_ON_BOTH_EDGES_BIT          0x4
01004 #define NI_GPCT_EDGE_GATE_MODE_MASK             0x18
01005 #define NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS     0x0
01006 #define NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS     0x8
01007 #define NI_GPCT_EDGE_GATE_STARTS_BITS           0x10
01008 #define NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS 0x18
01009 #define NI_GPCT_STOP_MODE_MASK                  0x60
01010 #define NI_GPCT_STOP_ON_GATE_BITS               0x00
01011 #define NI_GPCT_STOP_ON_GATE_OR_TC_BITS         0x20
01012 #define NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS  0x40
01013 #define NI_GPCT_LOAD_B_SELECT_BIT               0x80
01014 #define NI_GPCT_OUTPUT_MODE_MASK                0x300
01015 #define NI_GPCT_OUTPUT_TC_PULSE_BITS            0x100
01016 #define NI_GPCT_OUTPUT_TC_TOGGLE_BITS           0x200
01017 #define NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS   0x300
01018 #define NI_GPCT_HARDWARE_DISARM_MASK            0xc00
01019 #define NI_GPCT_NO_HARDWARE_DISARM_BITS         0x000
01020 #define NI_GPCT_DISARM_AT_TC_BITS               0x400
01021 #define NI_GPCT_DISARM_AT_GATE_BITS             0x800
01022 #define NI_GPCT_DISARM_AT_TC_OR_GATE_BITS       0xc00
01023 #define NI_GPCT_LOADING_ON_TC_BIT               0x1000
01024 #define NI_GPCT_LOADING_ON_GATE_BIT             0x4000
01025 #define NI_GPCT_COUNTING_MODE_MASK              0x7 << NI_GPCT_COUNTING_MODE_SHIFT
01026 #define NI_GPCT_COUNTING_MODE_NORMAL_BITS       0x0 << NI_GPCT_COUNTING_MODE_SHIFT
01027 #define NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS 0x1 << NI_GPCT_COUNTING_MODE_SHIFT
01028 #define NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS 0x2 << NI_GPCT_COUNTING_MODE_SHIFT
01029 #define NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS 0x3 << NI_GPCT_COUNTING_MODE_SHIFT
01030 #define NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS    0x4 << NI_GPCT_COUNTING_MODE_SHIFT
01031 #define NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS  0x6 << NI_GPCT_COUNTING_MODE_SHIFT
01032 #define NI_GPCT_INDEX_PHASE_MASK                0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT
01033 #define NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS    0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT
01034 #define NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS   0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT
01035 #define NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS   0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT
01036 #define NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS  0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT
01037 #define NI_GPCT_INDEX_ENABLE_BIT                0x400000
01038 #define NI_GPCT_COUNTING_DIRECTION_MASK         0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT
01039 #define NI_GPCT_COUNTING_DIRECTION_DOWN_BITS    0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT
01040 #define NI_GPCT_COUNTING_DIRECTION_UP_BITS      0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT
01041 #define NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT
01042 #define NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT
01043 #define NI_GPCT_RELOAD_SOURCE_MASK              0xc000000
01044 #define NI_GPCT_RELOAD_SOURCE_FIXED_BITS        0x0
01045 #define NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS    0x4000000
01046 #define NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS  0x8000000
01047 #define NI_GPCT_OR_GATE_BIT                     0x10000000
01048 #define NI_GPCT_INVERT_OUTPUT_BIT               0x20000000
01049 
01050 /* Bits for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC when
01051    using NI general-purpose counters. */
01052 #define NI_GPCT_CLOCK_SRC_SELECT_MASK           0x3f
01053 #define NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS       0x0
01054 #define NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS       0x1
01055 #define NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS       0x2
01056 #define NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS        0x3
01057 #define NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS        0x4
01058 #define NI_GPCT_NEXT_TC_CLOCK_SRC_BITS          0x5
01059 #define NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS     0x6 /* NI 660x-specific */
01060 #define NI_GPCT_PXI10_CLOCK_SRC_BITS            0x7
01061 #define NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS 0x8
01062 #define NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS 0x9
01063 #define NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK    0x30000000
01064 #define NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS      0x0
01065 #define NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS      0x10000000 /* divide source by 2 */
01066 #define NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS      0x20000000 /* divide source by 8 */
01067 #define NI_GPCT_INVERT_CLOCK_SRC_BIT            0x80000000
01068 #define NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(x)    (0x10 + x)
01069 #define NI_GPCT_RTSI_CLOCK_SRC_BITS(x)          (0x18 + x)
01070 #define NI_GPCT_PFI_CLOCK_SRC_BITS(x)           (0x20 + x)
01071 
01072 /* Possibilities for setting a gate source with
01073    INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
01074    May be bitwise-or'd with CR_EDGE or CR_INVERT. */
01075 /* M-series gates */
01076 #define NI_GPCT_TIMESTAMP_MUX_GATE_SELECT       0x0
01077 #define NI_GPCT_AI_START2_GATE_SELECT           0x12
01078 #define NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT    0x13
01079 #define NI_GPCT_NEXT_OUT_GATE_SELECT            0x14
01080 #define NI_GPCT_AI_START1_GATE_SELECT           0x1c
01081 #define NI_GPCT_NEXT_SOURCE_GATE_SELECT         0x1d
01082 #define NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT  0x1e
01083 #define NI_GPCT_LOGIC_LOW_GATE_SELECT           0x1f
01084 /* More gates for 660x */
01085 #define NI_GPCT_SOURCE_PIN_i_GATE_SELECT        0x100
01086 #define NI_GPCT_GATE_PIN_i_GATE_SELECT          0x101
01087 /* More gates for 660x "second gate" */
01088 #define NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT       0x201
01089 #define NI_GPCT_SELECTED_GATE_GATE_SELECT       0x21e
01090 /* M-series "second gate" sources are unknown, we should add them here
01091    with an offset of 0x300 when known. */
01092 #define NI_GPCT_DISABLED_GATE_SELECT            0x8000
01093 #define NI_GPCT_GATE_PIN_GATE_SELECT(x)         (0x102 + x)
01094 #define NI_GPCT_RTSI_GATE_SELECT(x)             NI_USUAL_RTSI_SELECT(x)
01095 #define NI_GPCT_PFI_GATE_SELECT(x)              NI_USUAL_PFI_SELECT(x)
01096 #define NI_GPCT_UP_DOWN_PIN_GATE_SELECT(x)      (0x202 + x)
01097 
01098 /* Possibilities for setting a source with INSN_CONFIG_SET_OTHER_SRC
01099    when using NI general-purpose counters. */
01100 #define NI_GPCT_SOURCE_ENCODER_A 0
01101 #define NI_GPCT_SOURCE_ENCODER_B 1
01102 #define NI_GPCT_SOURCE_ENCODER_Z 2
01103 /* M-series gates */
01104 /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */
01105 #define NI_GPCT_DISABLED_OTHER_SELECT   0x8000
01106 #define NI_GPCT_PFI_OTHER_SELECT(x) NI_USUAL_PFI_SELECT(x)
01107 
01108 /* Start sources for ni general-purpose counters for use with
01109    INSN_CONFIG_ARM */
01110 #define NI_GPCT_ARM_IMMEDIATE           0x0
01111 /* Start both the counter and the adjacent paired counter
01112    simultaneously */
01113 #define NI_GPCT_ARM_PAIRED_IMMEDIATE    0x1
01114 /* NI doesn't document bits for selecting hardware arm triggers.  If
01115    the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least significant
01116    bits (3 bits for 660x or 5 bits for m-series) through to the
01117    hardware. This will at least allow someone to figure out what the bits
01118    do later. */
01119 #define NI_GPCT_ARM_UNKNOWN             0x1000
01120 
01121 /* Digital filtering options for ni 660x for use with
01122    INSN_CONFIG_FILTER. */
01123 #define NI_GPCT_FILTER_OFF              0x0
01124 #define NI_GPCT_FILTER_TIMEBASE_3_SYNC  0x1
01125 #define NI_GPCT_FILTER_100x_TIMEBASE_1  0x2
01126 #define NI_GPCT_FILTER_20x_TIMEBASE_1   0x3
01127 #define NI_GPCT_FILTER_10x_TIMEBASE_1   0x4
01128 #define NI_GPCT_FILTER_2x_TIMEBASE_1    0x5
01129 #define NI_GPCT_FILTER_2x_TIMEBASE_3    0x6
01130 
01131 /* Master clock sources for ni mio boards and
01132    INSN_CONFIG_SET_CLOCK_SRC */
01133 #define NI_MIO_INTERNAL_CLOCK           0
01134 #define NI_MIO_RTSI_CLOCK               1
01135 /* Doesn't work for m-series, use NI_MIO_PLL_RTSI_CLOCK() the
01136    NI_MIO_PLL_* sources are m-series only */
01137 #define NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK 2
01138 #define NI_MIO_PLL_PXI10_CLOCK          3
01139 #define NI_MIO_PLL_RTSI0_CLOCK          4
01140 
01141 #define NI_MIO_PLL_RTSI_CLOCK(x) (NI_MIO_PLL_RTSI0_CLOCK + (x))
01142 
01143 /* Signals which can be routed to an NI RTSI pin with
01144    INSN_CONFIG_SET_ROUTING. The numbers assigned are not arbitrary, they
01145    correspond to the bits required to program the board. */
01146 #define NI_RTSI_OUTPUT_ADR_START1       0
01147 #define NI_RTSI_OUTPUT_ADR_START2       1
01148 #define NI_RTSI_OUTPUT_SCLKG            2
01149 #define NI_RTSI_OUTPUT_DACUPDN          3
01150 #define NI_RTSI_OUTPUT_DA_START1        4
01151 #define NI_RTSI_OUTPUT_G_SRC0           5
01152 #define NI_RTSI_OUTPUT_G_GATE0          6
01153 #define NI_RTSI_OUTPUT_RGOUT0           7
01154 #define NI_RTSI_OUTPUT_RTSI_BRD_0       8
01155 /* Pre-m-series always have RTSI clock on line 7 */
01156 #define NI_RTSI_OUTPUT_RTSI_OSC         12
01157 
01158 #define NI_RTSI_OUTPUT_RTSI_BRD(x) (NI_RTSI_OUTPUT_RTSI_BRD_0 + (x))
01159 
01160 
01161 int ni_tio_rinsn(struct ni_gpct *counter, a4l_kinsn_t *insn);
01162 int ni_tio_winsn(struct ni_gpct *counter, a4l_kinsn_t *insn);
01163 int ni_tio_insn_config(struct ni_gpct *counter, a4l_kinsn_t *insn);
01164 void ni_tio_init_counter(struct ni_gpct *counter);
01165 
01166 struct ni_gpct_device *ni_gpct_device_construct(a4l_dev_t * dev,
01167         void (*write_register) (struct ni_gpct * counter, unsigned int bits,
01168                 enum ni_gpct_register reg),
01169         unsigned int (*read_register) (struct ni_gpct * counter,
01170                 enum ni_gpct_register reg), enum ni_gpct_variant variant,
01171         unsigned int num_counters);
01172 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev);
01173 
01174 #if (defined(CONFIG_XENO_DRIVERS_ANALOGY_NI_MITE) || \
01175      defined(CONFIG_XENO_DRIVERS_ANALOGY_NI_MITE_MODULE))
01176 
01177 extern a4l_cmd_t ni_tio_cmd_mask;
01178 
01179 int ni_tio_input_inttrig(struct ni_gpct *counter, lsampl_t trignum);
01180 int ni_tio_cmd(struct ni_gpct *counter, a4l_cmd_t *cmd);
01181 int ni_tio_cmdtest(struct ni_gpct *counter, a4l_cmd_t *cmd);
01182 int ni_tio_cancel(struct ni_gpct *counter);
01183 
01184 void ni_tio_handle_interrupt(struct ni_gpct *counter, a4l_dev_t *dev);
01185 void ni_tio_set_mite_channel(struct ni_gpct *counter,
01186                              struct mite_channel *mite_chan);
01187 void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter,
01188                                     int *gate_error,
01189                                     int *tc_error,
01190                                     int *perm_stale_data, int *stale_data);
01191 
01192 #endif /* CONFIG_XENO_DRIVERS_ANALOGY_NI_MITE */
01193 
01194 #endif /* !__ANALOGY_NI_TIO_H__ */
ksrc/drivers/analogy/national_instruments/ni_tio.h
