00001
00057 #ifndef _RTTESTING_H
00058 #define _RTTESTING_H
00059
00060 #include <rtdm/rtdm.h>
00061
00062 typedef struct rttst_bench_res {
00063 long long avg;
00064 long min;
00065 long max;
00066 long overruns;
00067 long test_loops;
00068 } rttst_bench_res_t;
00069
00070 typedef struct rttst_interm_bench_res {
00071 struct rttst_bench_res last;
00072 struct rttst_bench_res overall;
00073 } rttst_interm_bench_res_t;
00074
00075 typedef struct rttst_overall_bench_res {
00076 struct rttst_bench_res result;
00077 long *histogram_avg;
00078 long *histogram_min;
00079 long *histogram_max;
00080 void *__padding;
00081 } rttst_overall_bench_res_t;
00082
00083
00084 #define RTTST_TMBENCH_TASK 0
00085 #define RTTST_TMBENCH_HANDLER 1
00086
00087 typedef struct rttst_tmbench_config {
00088 int mode;
00089 int priority;
00090 nanosecs_rel_t period;
00091 int warmup_loops;
00092 int histogram_size;
00093 int histogram_bucketsize;
00094 int freeze_max;
00095 } rttst_tmbench_config_t;
00096
00097
00098 #define RTTST_IRQBENCH_USER_TASK 0
00099 #define RTTST_IRQBENCH_KERNEL_TASK 1
00100 #define RTTST_IRQBENCH_HANDLER 2
00101 #define RTTST_IRQBENCH_HARD_IRQ 3
00102
00103 #define RTTST_IRQBENCH_SERPORT 0
00104 #define RTTST_IRQBENCH_PARPORT 1
00105
00106 typedef struct rttst_irqbench_config {
00107 int mode;
00108 int priority;
00109 int calibration_loops;
00110 unsigned int port_type;
00111 unsigned long port_ioaddr;
00112 unsigned int port_irq;
00113 } rttst_irqbench_config_t;
00114
00115 typedef struct rttst_irqbench_stats {
00116 unsigned long long irqs_received;
00117 unsigned long long irqs_acknowledged;
00118 } rttst_irqbench_stats_t;
00119
00120
00121 #define RTTST_SWTEST_FPU 0x1
00122 #define RTTST_SWTEST_USE_FPU 0x2
00123
00124 struct rttst_swtest_task {
00125 unsigned index;
00126 unsigned flags;
00127 };
00128
00129 struct rttst_swtest_dir {
00130 unsigned from;
00131 unsigned to;
00132 };
00133
00134 struct rttst_swtest_error {
00135 struct rttst_swtest_dir last_switch;
00136 unsigned fp_val;
00137 };
00138
00139
00140 #define RTIOC_TYPE_TESTING RTDM_CLASS_TESTING
00141
00145 #define RTDM_SUBCLASS_TIMERBENCH 0
00146 #define RTDM_SUBCLASS_IRQBENCH 1
00147 #define RTDM_SUBCLASS_SWITCHTEST 2
00148
00155 #define RTTST_RTIOC_INTERM_BENCH_RES \
00156 _IOWR(RTIOC_TYPE_TESTING, 0x00, struct rttst_interm_bench_res)
00157
00158
00159 #define RTTST_RTIOC_TMBENCH_START \
00160 _IOW(RTIOC_TYPE_TESTING, 0x10, struct rttst_tmbench_config)
00161
00162 #define RTTST_RTIOC_TMBENCH_STOP \
00163 _IOWR(RTIOC_TYPE_TESTING, 0x11, struct rttst_overall_bench_res)
00164
00165
00166 #define RTTST_RTIOC_IRQBENCH_START \
00167 _IOW(RTIOC_TYPE_TESTING, 0x20, struct rttst_irqbench_config)
00168
00169 #define RTTST_RTIOC_IRQBENCH_STOP \
00170 _IO(RTIOC_TYPE_TESTING, 0x21)
00171
00172 #define RTTST_RTIOC_IRQBENCH_GET_STATS \
00173 _IOR(RTIOC_TYPE_TESTING, 0x22, struct rttst_irqbench_stats)
00174
00175 #define RTTST_RTIOC_IRQBENCH_WAIT_IRQ \
00176 _IO(RTIOC_TYPE_TESTING, 0x23)
00177
00178 #define RTTST_RTIOC_IRQBENCH_REPLY_IRQ \
00179 _IO(RTIOC_TYPE_TESTING, 0x24)
00180
00181
00182 #define RTTST_RTIOC_SWTEST_SET_TASKS_COUNT \
00183 _IOW(RTIOC_TYPE_TESTING, 0x30, unsigned long)
00184
00185 #define RTTST_RTIOC_SWTEST_SET_CPU \
00186 _IOW(RTIOC_TYPE_TESTING, 0x31, unsigned long)
00187
00188 #define RTTST_RTIOC_SWTEST_REGISTER_UTASK \
00189 _IOW(RTIOC_TYPE_TESTING, 0x32, struct rttst_swtest_task)
00190
00191 #define RTTST_RTIOC_SWTEST_CREATE_KTASK \
00192 _IOWR(RTIOC_TYPE_TESTING, 0x33, struct rttst_swtest_task)
00193
00194 #define RTTST_RTIOC_SWTEST_PEND \
00195 _IOR(RTIOC_TYPE_TESTING, 0x34, struct rttst_swtest_task)
00196
00197 #define RTTST_RTIOC_SWTEST_SWITCH_TO \
00198 _IOR(RTIOC_TYPE_TESTING, 0x35, struct rttst_swtest_dir)
00199
00200 #define RTTST_RTIOC_SWTEST_GET_SWITCHES_COUNT \
00201 _IOR(RTIOC_TYPE_TESTING, 0x36, unsigned long)
00202
00203 #define RTTST_RTIOC_SWTEST_GET_LAST_ERROR \
00204 _IOR(RTIOC_TYPE_TESTING, 0x37, struct rttst_swtest_error)
00205
00209 #endif